India has emerged as a global hub for semiconductor design and R&D

1. At a Glance

• India hosts ~7% of global Semiconductor-domain Global Capability Centres (GCCs) and employs ~20% of the world's chip-design workforce [S1].
• Strategy anchored in Atmanirbhar Bharat and Make in India, Make for the World, targeting the full stack: R&D → Design → Fab → ATMP → talent [S1].
• Examinable for GS-III (Economy, S&T) — flagship execution vehicle is the India Semiconductor Mission (ISM) under MeitY [S2][S5].

2. Why in the News

• PIB release, 13 March 2026: MeitY declared India a "global hub for semiconductor design and R&D" with the 7% GCC / 20% workforce metrics [S1].
• Aug 2025: PIB feature "Powering the Future: The Semiconductor and AI Revolution" [S6].
• 2024-25: Cabinet cleared additional fab/ATMP units; FSA signed for India's first commercial fab at Dholera [S4][S5][S7].

3. Background & Evolution

• Dec 2021: Cabinet approves the Programme for Development of Semiconductors and Display Manufacturing Ecosystem with outlay of ₹76,000 crore [S8].
• Dec 2021: Design Linked Incentive (DLI) Scheme launched; C-DAC as nodal agency [S2].
• 2022: India Semiconductor Mission (ISM) set up as an independent business division under Digital India Corporation [S2].
• Feb 2024: Cabinet approves three units — Tata-PSMC fab (Dholera), TSAT (Morigaon, Assam), CG Power-Renesas (Sanand) [S4].
• 13 March 2024: PM lays foundation stones for 3 semiconductor facilities worth ~₹1.25 lakh crore ("India's Techade: Chips for Viksit Bharat") [S7].
• March 2025: FSA signed for Tata Electronics fab at Dholera (₹91,000 crore; 50,000 WSPM) [S4][S5].
• 2025-26: ISM 2.0 narrative; additional units approved (₹3,900 crore cumulative for two units) [S5].

4. Core Static Facts

• Implementing Ministry: Ministry of Electronics & IT (MeitY); nodal body — India Semiconductor Mission (ISM) [S1][S2].
• DLI nodal agency: C-DAC [S2].
• DLI incentives: Product DLI up to 50% of eligible expenditure capped at ₹15 cr/application; Deployment DLI 6%→4% of net sales over 5 yrs, capped ₹30 cr [S2].
• DLI sanctioned projects: 23 chip-design projects [S2].
• Programme outlay (2021): ₹76,000 crore [S8].
• Approved fab/ATMP units:
• Tata Electronics, Dholera, Gujarat — ₹91,000 cr, 50,000 WSPM (first commercial fab) [S4][S5].
• Micron, Sanand, Gujarat — ATMP, ₹13,000 cr [S5].
• TSAT (Tata), Morigaon, Assam — ₹27,000 cr [S4].
• CG Power + Renesas (Japan) + Stars Microelectronics (Thailand) — Sanand, ₹7,600 cr [S4].
• Workforce share: ~20% of global chip-design talent in India [S1].
• GCC share: ~7% of global semiconductor GCCs hosted in India [S1].

5. Multi-Dimensional Analysis

Economic - Cumulative committed investment crosses ₹1.5 lakh crore across approved units, anchoring Gujarat & Assam as electronics clusters [S4][S5][S7]. - Reduces import dependence in a sector projected to drive AI, EV, telecom value chains [S6].

Scientific / Technological - DLI targets ICs, chipsets, SoCs, IP cores across full design lifecycle [S2]. - R&D treated as foundational: drives cost efficiency, performance, reliability [S1].

Geopolitical / Strategic - Joint ventures with Japan (Renesas), Thailand, Taiwan (PSMC), US (Micron) signal supply-chain diversification away from China [S4][S5]. - Aligns with Quad semiconductor supply-chain initiatives.

Administrative / Federal - Centre-State co-financing: Gujarat & Assam offered land + state-level incentives layered on central fiscal support [S4][S5]. - ISM operates as a specialised division — single-window for fiscal support agreements [S5].

Social - Talent pipeline via Chips to Startup (C2S) and academia tie-ups embedded in DLI [S2].

6. Recent Developments (last 12-18 months)

• March 2026 (PIB): India formally branded global semiconductor design hub; 7% GCC / 20% workforce data released [S1].
• Aug 2025: PIB monograph "Semiconductor and AI Revolution" [S6].
• March 2025: Fiscal Support Agreement signed Tata–ISM for Dholera fab [S5].
• 2024-25: Cabinet approval of two additional units, ~₹3,900 crore [S5].
• Feb 2026: ISM 2.0 document released [S3].
• 13 March 2024: Foundation stones for 3 facilities worth ₹1.25 lakh crore [S7].

7. Prelims Hooks

• India hosts ~7% of global semiconductor GCCs [S1].
• India employs ~20% of the global chip-design workforce [S1].
• ISM functions under MeitY, not DST or DSIR [S1][S2].
• DLI Scheme launched December 2021 [S2].
• C-DAC is the nodal agency for DLI [S2].
• DLI product incentive ceiling: ₹15 crore per application [S2].
• 23 chip-design projects sanctioned under DLI [S2].
• Semicon Programme outlay (2021): ₹76,000 crore [S8].
• India's first commercial fab: Tata Electronics, Dholera SIR, Gujarat — 50,000 WSPM [S4][S5].
• Micron's ATMP unit is at Sanand, Gujarat (₹13,000 crore) [S5].
• TSAT (Tata) ATMP is at Morigaon, Assam (₹27,000 crore) [S4].
• CG Power's partners: Renesas (Japan) and Stars Microelectronics (Thailand) [S4].
• "India's Techade: Chips for Viksit Bharat" foundation event: 13 March 2024, ~₹1.25 lakh crore [S7].

8. Mains Relevance

• GS-III: Indian Economy — Industrial Policy; Science & Technology — indigenisation; Infrastructure.
• GS-II: Government policies/interventions; bilateral cooperation (Japan, US, Taiwan).
• Probable stems: 1. "Discuss how the India Semiconductor Mission seeks to position India in the global semiconductor value chain. What are the strategic vulnerabilities that persist?" 2. "India's strength in chip design has not translated into manufacturing leadership. Examine the policy correctives since 2021." 3. "Critically evaluate the Design Linked Incentive (DLI) Scheme in catalysing a self-reliant semiconductor ecosystem."

9. Related Topics to Study Next

• PLI Scheme — Electronics & IT hardware: parallel manufacturing push.
• Make in India / Atmanirbhar Bharat: policy umbrella [S1].
• Global Capability Centres (GCCs): services-to-design transition.
• National Quantum Mission / IndiaAI Mission: compute-stack dependencies.
• Quad Semiconductor Supply Chain Initiative: geopolitics.
• Rare Earths & Critical Minerals policy: upstream input security.
• C-DAC and Chips-to-Startup (C2S): talent pipeline [S2].
• STPI / SEZ Act: Dholera SEZ notification basis [S9].

10. Common Errors / Trap Areas

• ISM is under MeitY, NOT DST/DSIR/DPIIT.
• DLI nodal agency is C-DAC, not ISM itself or MeitY directly [S2].
• Micron's Sanand unit is ATMP (packaging), not a fab — the first fab is Tata's Dholera [S5].
• Dholera fab capacity is 50,000 WSPM, not "50,000 wafers per year" [S5].
• The 2021 outlay ₹76,000 cr is for the umbrella programme; do not conflate with the ₹1.25 lakh cr investment commitment of March 2024 [S7][S8].

11. Sources

• [S1] India has emerged as a global hub for semiconductor design and R&D — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2239608 — (tier 1)
• [S2] Government pushes semiconductor design innovation with the DLI Scheme — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2159727 — (tier 1)
• [S3] India Semiconductor Mission 2.0 — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2224839 — (tier 1)
• [S4] Cabinet approves three more semiconductor units — https://www.pib.gov.in/PressReleaseIframePage.aspx?PRID=2010135 — (tier 1)
• [S5] ISM–Tata Electronics–TSMPL Fiscal Support Agreement for Dholera Fab — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2108602 — (tier 1)
• [S6] Powering the Future: The Semiconductor and AI Revolution (15 Aug 2025) — https://static.pib.gov.in/WriteReadData/specificdocs/documents/2025/aug/doc2025815613001.pdf — (tier 1)
• [S7] PM to lay foundation stone of three semiconductor facilities (~₹1.25 lakh cr) — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2013750 — (tier 1)
• [S8] Cabinet approves Programme for Semiconductors and Display Manufacturing Ecosystem — https://www.pib.gov.in/PressReleasePage.aspx?PRID=1781723 — (tier 1)
• [S9] Government Notifies India's First Chip Fabrication Plant at SEZ Dholera — https://www.pib.gov.in/PressReleasePage.aspx?PRID=2252649 — (tier 1)